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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] - Rev 112

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112 Modified comment. olivier.girard 4799d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4800d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4855d 23h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4871d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4875d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4889d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4911d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4912d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4917d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4963d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4966d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4966d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/

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