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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] - Rev 155

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4266d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4351d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4354d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
136 Update all FPGA projects with the latest core version. olivier.girard 4473d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4486d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4570d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
112 Modified comment. olivier.girard 4779d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4780d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4836d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4851d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4855d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4869d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4892d 06h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4892d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4897d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4943d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4946d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4946d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/

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