URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] - Rev 91

Rev	Log message	Author	Age	Path
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4974d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4997d 04h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/
85	Diverse RTL cosmetic updates.	olivier.girard	4997d 06h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5002d 07h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5051d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/