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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] - Rev 107

Rev	Log message	Author	Age	Path
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4902d 07h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4917d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4927d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4931d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	5009d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5012d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/