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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] - Rev 98

Rev	Log message	Author	Age	Path
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	5012d 05h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	5016d 05h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	5094d 05h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5097d 12h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/