URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [bin/] - Rev 162

Rev	Log message	Author	Age	Path
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4417d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4508d 02h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/
136	Update all FPGA projects with the latest core version.	olivier.girard	4539d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4927d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4931d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5013d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/