OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 72

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
72 Expand configurability options of the program and data memory sizes. olivier.girard 5060d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5207d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
61 Update openMSP430 rtl. olivier.girard 5239d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5240d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5246d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
40 Minor updates. olivier.girard 5275d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5275d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
37 olivier.girard 5275d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
36 Remove old core version. olivier.girard 5275d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5285d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.
olivier.girard 5285d 10h /openmsp430/trunk/fpga/diligent_s3board/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5375d 07h /openmsp430/trunk/fpga/diligent_s3board/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5375d 07h /openmsp430/trunk/fpga/diligent_s3board/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5396d 05h /openmsp430/trunk/fpga/diligent_s3board/
20 added some SVN ignore patterns.
small update to html documentation
olivier.girard 5422d 00h /openmsp430/trunk/fpga/diligent_s3board/
16 Updated header with SVN info olivier.girard 5422d 01h /openmsp430/trunk/fpga/diligent_s3board/
5 Added some ignore pattern properties... olivier.girard 5444d 02h /openmsp430/trunk/fpga/diligent_s3board/
3 update FPGA inc file to match the CORE version olivier.girard 5456d 13h /openmsp430/trunk/fpga/diligent_s3board/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5457d 01h /openmsp430/trunk/fpga/diligent_s3board/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.