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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 84

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Rev Log message Author Age Path
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4905d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4966d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5053d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5079d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5081d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5227d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
61 Update openMSP430 rtl. olivier.girard 5259d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5261d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5267d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
40 Minor updates. olivier.girard 5295d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5295d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
37 olivier.girard 5295d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
36 Remove old core version. olivier.girard 5295d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5306d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5306d 07h /openmsp430/trunk/fpga/diligent_s3board/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5396d 04h /openmsp430/trunk/fpga/diligent_s3board/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5396d 04h /openmsp430/trunk/fpga/diligent_s3board/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5417d 02h /openmsp430/trunk/fpga/diligent_s3board/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5442d 21h /openmsp430/trunk/fpga/diligent_s3board/
16 Updated header with SVN info olivier.girard 5442d 22h /openmsp430/trunk/fpga/diligent_s3board/

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