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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] - Rev 111

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Rev Log message Author Age Path
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4813d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4888d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4894d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4898d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
37 olivier.girard 5320d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5330d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5441d 08h /openmsp430/trunk/fpga/diligent_s3board/bench/
16 Updated header with SVN info olivier.girard 5467d 04h /openmsp430/trunk/fpga/diligent_s3board/bench/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5502d 03h /openmsp430/trunk/fpga/diligent_s3board/bench/

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