URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] - Rev 109

Rev	Log message	Author	Age	Path
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4899d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4905d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4909d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
37		olivier.girard	5331d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5341d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5452d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
16	Updated header with SVN info	olivier.girard	5478d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5513d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/