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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] - Rev 143

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143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4433d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
136 Update all FPGA projects with the latest core version. olivier.girard 4481d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4788d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4863d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4869d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4873d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
37 olivier.girard 5295d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5306d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5417d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
16 Updated header with SVN info olivier.girard 5442d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5477d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/

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