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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 162

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4265d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4350d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4354d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
136 Update all FPGA projects with the latest core version. olivier.girard 4473d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4486d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4570d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
112 Modified comment. olivier.girard 4779d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4780d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4834d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4851d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4855d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4869d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4891d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4892d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4897d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4958d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5045d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5072d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5219d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
61 Update openMSP430 rtl. olivier.girard 5250d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/

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