URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 54

Rev	Log message	Author	Age	Path
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5278d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37		olivier.girard	5307d 12h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36	Remove old core version.	olivier.girard	5307d 12h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5317d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5317d 20h	/openmsp430/trunk/fpga/diligent_s3board/rtl/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5428d 16h	/openmsp430/trunk/fpga/diligent_s3board/rtl/
16	Updated header with SVN info	olivier.girard	5454d 12h	/openmsp430/trunk/fpga/diligent_s3board/rtl/
3	update FPGA inc file to match the CORE version	olivier.girard	5488d 23h	/openmsp430/trunk/fpga/diligent_s3board/rtl/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5489d 11h	/openmsp430/trunk/fpga/diligent_s3board/rtl/