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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 84

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84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4904d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4965d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5052d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5079d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5226d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
61 Update openMSP430 rtl. olivier.girard 5258d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5260d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5265d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37 olivier.girard 5294d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36 Remove old core version. olivier.girard 5294d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5304d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5304d 16h /openmsp430/trunk/fpga/diligent_s3board/rtl/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5415d 12h /openmsp430/trunk/fpga/diligent_s3board/rtl/
16 Updated header with SVN info olivier.girard 5441d 07h /openmsp430/trunk/fpga/diligent_s3board/rtl/
3 update FPGA inc file to match the CORE version olivier.girard 5475d 19h /openmsp430/trunk/fpga/diligent_s3board/rtl/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5476d 07h /openmsp430/trunk/fpga/diligent_s3board/rtl/

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