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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 94

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Rev Log message Author Age Path
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4884d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4907d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4907d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4912d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4973d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5060d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5087d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5234d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
61 Update openMSP430 rtl. olivier.girard 5266d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5268d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5273d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37 olivier.girard 5302d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36 Remove old core version. olivier.girard 5302d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5312d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5312d 14h /openmsp430/trunk/fpga/diligent_s3board/rtl/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5423d 09h /openmsp430/trunk/fpga/diligent_s3board/rtl/
16 Updated header with SVN info olivier.girard 5449d 05h /openmsp430/trunk/fpga/diligent_s3board/rtl/
3 update FPGA inc file to match the CORE version olivier.girard 5483d 17h /openmsp430/trunk/fpga/diligent_s3board/rtl/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5484d 05h /openmsp430/trunk/fpga/diligent_s3board/rtl/

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