URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 36

Rev	Log message	Author	Age	Path
36	Remove old core version.	olivier.girard	5431d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5442d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5442d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5552d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
16	Updated header with SVN info	olivier.girard	5578d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
3	update FPGA inc file to match the CORE version	olivier.girard	5613d 04h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5613d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/