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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 59

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59 Update the FPGA projects with the latest core design updates. olivier.girard 5260d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5265d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
37 olivier.girard 5294d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
36 Remove old core version. olivier.girard 5294d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5304d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5304d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5415d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
16 Updated header with SVN info olivier.girard 5441d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
3 update FPGA inc file to match the CORE version olivier.girard 5475d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5476d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/

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