OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5050d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5077d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5224d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
61 Update openMSP430 rtl. olivier.girard 5256d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5258d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5263d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
37 olivier.girard 5292d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
36 Remove old core version. olivier.girard 5292d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5302d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5302d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5413d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
16 Updated header with SVN info olivier.girard 5439d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
3 update FPGA inc file to match the CORE version olivier.girard 5473d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5474d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.