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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] - Rev 91

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Rev Log message Author Age Path
85 Diverse RTL cosmetic updates. olivier.girard 5028d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5094d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5181d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/
37 olivier.girard 5423d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5423d 14h /openmsp430/trunk/core/rtl/verilog/periph/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5544d 16h /openmsp430/trunk/core/rtl/verilog/periph/
17 Updated header with SVN info olivier.girard 5570d 11h /openmsp430/trunk/core/rtl/verilog/periph/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5605d 11h /openmsp430/trunk/core/rtl/verilog/periph/

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