OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] - Rev 111

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4847d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4901d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4918d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4928d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4932d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
85 Diverse RTL cosmetic updates. olivier.girard 4959d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5137d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5139d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5286d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5325d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
40 Minor updates. olivier.girard 5354d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5354d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
37 olivier.girard 5354d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5364d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5364d 15h /openmsp430/trunk/fpga/diligent_s3board/sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5475d 11h /openmsp430/trunk/fpga/diligent_s3board/sim/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5501d 05h /openmsp430/trunk/fpga/diligent_s3board/sim/
16 Updated header with SVN info olivier.girard 5501d 06h /openmsp430/trunk/fpga/diligent_s3board/sim/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5536d 06h /openmsp430/trunk/fpga/diligent_s3board/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.