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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] - Rev 213

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212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3156d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
202 Add DMA interface support + LINT cleanup olivier.girard 3294d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4283d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4338d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4368d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4459d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
136 Update all FPGA projects with the latest core version. olivier.girard 4490d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4797d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4852d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4868d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4878d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4882d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
85 Diverse RTL cosmetic updates. olivier.girard 4909d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5087d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5090d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5236d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5276d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
40 Minor updates. olivier.girard 5304d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5304d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
37 olivier.girard 5304d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/

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