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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] - Rev 162

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4269d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4324d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4354d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4445d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
136 Update all FPGA projects with the latest core version. olivier.girard 4476d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4783d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4838d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4854d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4864d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4868d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
85 Diverse RTL cosmetic updates. olivier.girard 4895d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5073d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5075d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5222d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5261d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
40 Minor updates. olivier.girard 5290d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5290d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
37 olivier.girard 5290d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5301d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5301d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/

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