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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] - Rev 61

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54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5313d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
40 Minor updates. olivier.girard 5341d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5341d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
37 olivier.girard 5341d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5352d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5352d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5463d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5488d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
16 Updated header with SVN info olivier.girard 5488d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5523d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/

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