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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] - Rev 72

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72 Expand configurability options of the program and data memory sizes. olivier.girard 5119d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5266d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5305d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
40 Minor updates. olivier.girard 5334d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5334d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
37 olivier.girard 5334d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5345d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5345d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5456d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5481d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
16 Updated header with SVN info olivier.girard 5481d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5516d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/

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