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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [bin/] - Rev 153

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151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4470d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4561d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
136 Update all FPGA projects with the latest core version. olivier.girard 4592d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4980d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4984d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5189d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5191d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
37 olivier.girard 5406d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5417d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5417d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5527d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
16 Updated header with SVN info olivier.girard 5553d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5588d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/

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