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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [run/] - Rev 212

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Rev	Log message	Author	Age	Path
212	Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains.	olivier.girard	3275d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
153	Update XFLOW scripts to bring more automation. Several bitstreams are now checked in for direct use.	olivier.girard	4457d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4578d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
136	Update all FPGA projects with the latest core version.	olivier.girard	4609d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5395d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
40	Minor updates.	olivier.girard	5423d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5423d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
37		olivier.girard	5423d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5434d 06h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
20	added some SVN ignore patterns. small update to html documentation	olivier.girard	5570d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5605d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/

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