URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [run/] - Rev 136

Rev	Log message	Author	Age	Path
136	Update all FPGA projects with the latest core version.	olivier.girard	4492d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5277d 11h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
40	Minor updates.	olivier.girard	5306d 07h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5306d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
37		olivier.girard	5306d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5316d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
20	added some SVN ignore patterns. small update to html documentation	olivier.girard	5453d 07h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5488d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/