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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3284d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4273d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4328d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
136 Update all FPGA projects with the latest core version. olivier.girard 4480d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4787d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4842d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4858d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
85 Diverse RTL cosmetic updates. olivier.girard 4899d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5226d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
37 olivier.girard 5294d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5305d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5305d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5416d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
16 Updated header with SVN info olivier.girard 5441d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5476d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/

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