URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] - Rev 23

Rev	Log message	Author	Age	Path
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5554d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
16	Updated header with SVN info	olivier.girard	5579d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5614d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/