URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] - Rev 37

Rev	Log message	Author	Age	Path
37		olivier.girard	5423d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5434d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5434d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5544d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
16	Updated header with SVN info	olivier.girard	5570d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5605d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/