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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] - Rev 106

Rev	Log message	Author	Age	Path
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4982d 12h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5043d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5365d 13h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5443d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
5	Added some ignore pattern properties...	olivier.girard	5602d 14h	/openmsp430/trunk/fpga/diligent_s3board/software/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5615d 12h	/openmsp430/trunk/fpga/diligent_s3board/software/