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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] - Rev 202

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Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3266d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4131d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4255d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4310d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4414d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
136 Update all FPGA projects with the latest core version. olivier.girard 4462d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4825d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4886d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5208d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5286d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
5 Added some ignore pattern properties... olivier.girard 5445d 07h /openmsp430/trunk/fpga/diligent_s3board/software/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5458d 05h /openmsp430/trunk/fpga/diligent_s3board/software/

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