OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] - Rev 212

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3127d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
202 Add DMA interface support + LINT cleanup olivier.girard 3265d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
179 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4130d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4254d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4309d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4414d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
136 Update all FPGA projects with the latest core version. olivier.girard 4461d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4824d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4886d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5208d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5286d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
5 Added some ignore pattern properties... olivier.girard 5445d 00h /openmsp430/trunk/fpga/diligent_s3board/software/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5457d 23h /openmsp430/trunk/fpga/diligent_s3board/software/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.