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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] - Rev 204

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4370d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4425d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
136 Update all FPGA projects with the latest core version. olivier.girard 4577d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4884d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4939d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5174d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5323d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
37 olivier.girard 5391d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5401d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5401d 23h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5491d 21h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5491d 21h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5512d 19h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
16 Updated header with SVN info olivier.girard 5538d 14h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
5 Added some ignore pattern properties... olivier.girard 5560d 16h /openmsp430/trunk/fpga/diligent_s3board/synthesis/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5573d 14h /openmsp430/trunk/fpga/diligent_s3board/synthesis/

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