URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] - Rev 25

Rev	Log message	Author	Age	Path
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5503d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5503d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5523d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
16	Updated header with SVN info	olivier.girard	5549d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
5	Added some ignore pattern properties...	olivier.girard	5571d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5584d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/