| Rev |
Log message |
Author |
Age |
Path |
| 868 |
Declare du_flush_pipe in or1200_top
Signed-off-by: Olof Kindgren <olof at opencores.org> |
olof |
3701d 04h |
/openrisc/ |
| 867 |
Publish OR1K 1.1 architecture spec
Changelog:
- Add atomicity chapter.
- Add l.lwa and l.swa instructions. |
stekern |
3828d 01h |
/openrisc/ |
| 866 |
orpsocv2: correct build/par issue on Atlys board
From patch submission e-mail:
The first of the series is an issue that has been around since the
beginning (at least based on the svn log files) and traces its root to the
first Xilinx board supported by orpsocv2, the ML501. Apparently Makefile
for the final place-and-route process in all the builds contains a typo
which leads to the routing tool not using any timing constraint at all.
Patch by: Jason Zheng <jxzheng@gmail.com> |
stekern |
3848d 06h |
/openrisc/ |
| 865 |
Raise illegal instruction exception when l.ror is not implemented
Instead of throwing an illegal instruction exception when the rotate
instructions are disabled (OR1200_ALU_IMPL_ROTATE is undefined), another
instruction (slr?) was executed instead.
This closes bug 97
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4032d 02h |
/openrisc/ |
| 864 |
ORPSoC: Merge display_arch_state tasks
or1200-monitor contains the tasks display_arch_state and display_arch_state_except which are almost identical. This patch merges these two tasks into one, with a parameter to specify whether it should print out "(exception)" or not
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
4124d 13h |
/openrisc/ |
| 863 |
ORPSoC: Add paramers to or1200-monitor for setting name and path of log files
Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
4130d 17h |
/openrisc/ |
| 862 |
sysc: avoid using orpsoc internal classes directly
The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api. |
stekern |
4141d 09h |
/openrisc/ |
| 861 |
sysc: include unistd.h
write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail |
stekern |
4141d 09h |
/openrisc/ |
| 860 |
or1200_monitor.v: Remove trailing whitespace |
olof |
4145d 14h |
/openrisc/ |
| 859 |
Execute trapped instruction after breakpoint is removed
Closes bug #104
When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.
Proposed solution:
- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).
- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).
Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org> |
olof |
4145d 16h |
/openrisc/ |
| 858 |
orpsoc/tests: Fix or1200-dsxinsn when caches are not present
This test would go into an endless loop when caches are not present. |
stekern |
4245d 21h |
/openrisc/ |
| 857 |
orpsocv2: remove reference to r32 in context save/restore |
julius |
4255d 12h |
/openrisc/ |
| 856 |
Fixed rounding of UART divisor |
skrzyp |
4299d 15h |
/openrisc/ |
| 855 |
Publish OR1K 1.0 architecture spec |
julius |
4342d 14h |
/openrisc/ |
| 854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4352d 07h |
/openrisc/ |
| 853 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4377d 16h |
/openrisc/ |
| 852 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4377d 16h |
/openrisc/ |
| 851 |
changed branch delay flags |
skrzyp |
4380d 16h |
/openrisc/ |
| 850 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4392d 08h |
/openrisc/ |
| 849 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4392d 08h |
/openrisc/ |
