OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 117

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5227d 04h /openrisc/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5227d 04h /openrisc/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5228d 04h /openrisc/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5228d 05h /openrisc/
113 Updates to exception handling for l.add and l.div jeremybennett 5229d 04h /openrisc/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5229d 04h /openrisc/
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5229d 08h /openrisc/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5230d 05h /openrisc/
109 or_debug_proxy does signals with signals, just ignores signals julius 5230d 13h /openrisc/
108 Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu. jeremybennett 5232d 03h /openrisc/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5232d 04h /openrisc/
106 Removing old tests, pending addition of new ones. jeremybennett 5232d 04h /openrisc/
105 Tagging the 0.4.0rc1 candidate release of Or1ksim jeremybennett 5235d 12h /openrisc/
104 Candidate release 0.4.0rc4 jeremybennett 5235d 12h /openrisc/
103 Updated to clarify lf.madd.d and lf.madd.s opcodes. jeremybennett 5236d 08h /openrisc/
102 added linux-2.6.34 and uClibc-0.9.31 patch file marcus.erlandsson 5242d 15h /openrisc/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5244d 06h /openrisc/
100 Single precision FPU stuff for or1ksim julius 5244d 08h /openrisc/
99 Bug in test evaluation for library fixed. jeremybennett 5249d 06h /openrisc/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5250d 07h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.