OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 269

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
269 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 14h /openrisc/
268 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 14h /openrisc/
267 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 14h /openrisc/
266 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 15h /openrisc/
265 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 15h /openrisc/
264 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 15h /openrisc/
263 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5076d 15h /openrisc/
262 Baseline port of GCC 4.5.1 for OpenRISC 1000. jeremybennett 5076d 15h /openrisc/
261 Linux patch update - all ioremap calls now default with cache inhibit julius 5078d 04h /openrisc/
260 Fixed `define in FPU that didnt need to be there julius 5078d 05h /openrisc/
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5080d 00h /openrisc/
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5080d 01h /openrisc/
257 Changed or1200 supplementary manual from referring or or1200v2 to be just for the or1200 in general julius 5080d 11h /openrisc/
256 Linux patch update - disabled SCET driver by default julius 5081d 06h /openrisc/
255 Linux patch update with USB host data cache issue solved, file formatting fixed julius 5083d 08h /openrisc/
254 Update of Linux patch with USB driver, rename of its or1ksim config file julius 5084d 01h /openrisc/
253 No need to define PROTOTYPES, now DWARF 2 debugging is the default. jeremybennett 5084d 12h /openrisc/
252 Changes to use source and line info when DWARF debug data is available. jeremybennett 5084d 12h /openrisc/
251 Bug in register enum declaration fixed in or32. Bug with empty arguments to
macro VEC_TA_GTY fixed.

* config/or32/or32.h <enum reg_class>: CR_REGS removed from
enumeration.
* vec.h: All references to VEC_TA_GTY with an empty fourth
argument replaced by VEC_TA_GTY_ANON with only three arguments
<VEC_TA_GTY_ANON>: Created.
jeremybennett 5084d 12h /openrisc/
250 Specify -DPROTOTYPES to work round problems with K&R style declarations in GDB
testsuite.
jeremybennett 5085d 16h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.