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Rev Log message Author Age Path
271 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 08h /openrisc/
270 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 08h /openrisc/
269 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 08h /openrisc/
268 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 08h /openrisc/
267 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 08h /openrisc/
266 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 09h /openrisc/
265 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 09h /openrisc/
264 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 09h /openrisc/
263 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5176d 09h /openrisc/
262 Baseline port of GCC 4.5.1 for OpenRISC 1000. jeremybennett 5176d 10h /openrisc/
261 Linux patch update - all ioremap calls now default with cache inhibit julius 5177d 23h /openrisc/
260 Fixed `define in FPU that didnt need to be there julius 5177d 23h /openrisc/
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5179d 19h /openrisc/
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5179d 19h /openrisc/
257 Changed or1200 supplementary manual from referring or or1200v2 to be just for the or1200 in general julius 5180d 05h /openrisc/
256 Linux patch update - disabled SCET driver by default julius 5181d 00h /openrisc/
255 Linux patch update with USB host data cache issue solved, file formatting fixed julius 5183d 02h /openrisc/
254 Update of Linux patch with USB driver, rename of its or1ksim config file julius 5183d 19h /openrisc/
253 No need to define PROTOTYPES, now DWARF 2 debugging is the default. jeremybennett 5184d 06h /openrisc/
252 Changes to use source and line info when DWARF debug data is available. jeremybennett 5184d 06h /openrisc/

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