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400 Updates to the linker, GCC, newlib and GDB in preparation for supporting C++. The key changes are that the linker now uses RELA and that GCC may save registers at the bottom of the stack before the frame is allocated or after it is deallocated, so exception handlers/thread primitives should not use the first 130 bytes after the SP. jeremybennett 5012d 07h /openrisc/
399 Updates to the linker, GCC, newlib and GDB in preparation for supporting C++. The key changes are that the linker now uses RELA and that GCC may save registers at the bottom of the stack before the frame is allocated or after it is deallocated, so exception handlers/thread primitives should not use the first 130 bytes after the SP. jeremybennett 5012d 10h /openrisc/
398 ORPSoCv2 removing generic backend path - not needed julius 5013d 09h /openrisc/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 5014d 08h /openrisc/
396 ORPSoCv2 final software fixes...for now. See updated README julius 5017d 07h /openrisc/
395 ORPSoCv2 moving ethernet tests to correct place julius 5017d 07h /openrisc/
394 ORPSoCv2 removing unused directories julius 5017d 07h /openrisc/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5017d 07h /openrisc/
392 ORPSoCv2 software path reorganisation stage 1. julius 5017d 23h /openrisc/
391 Removing modules no longer needed in ORPSoCv2 julius 5019d 00h /openrisc/
390 Updated toolchain build scripts to use FTP server on OpenCores.org. julius 5019d 00h /openrisc/
389 SD-Card boot added (sdboot) to the commands in the load file. DOS-filesystem added to support Fat12-16. Driver for SD-card added, SD and SDHC supported
Currently hardcoded to boot from vmlinux.bin		 tac2 5029d 08h /openrisc/
388 Tagging the 0.5.0rc2 candidate release of Or1ksim jeremybennett 5042d 06h /openrisc/
387 Fixed testing, to always use our DEJAGNU config. jeremybennett 5042d 07h /openrisc/
386 Updated for release 0.5.0rc2 jeremybennett 5042d 07h /openrisc/
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5042d 07h /openrisc/
384 Tagging the 1.0rc2 candidate release of GCC 4.5.1 jeremybennett 5043d 08h /openrisc/
383 Adding makeinfo as a required tool to crossbuild-1.0.sh script julius 5043d 11h /openrisc/
382 New uClibc patch - to be built with 1.0 toolchain julius 5044d 05h /openrisc/
381 Crossbuild script for 1.0 updated to use new GCC rc2 patch and linux-2.6.35 julius 5044d 05h /openrisc/

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