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Rev Log message Author Age Path
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4935d 22h /openrisc/
433 New single program interrupt test programs. jeremybennett 4937d 00h /openrisc/
432 Updates to handle interrupts correctly. jeremybennett 4937d 01h /openrisc/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4939d 00h /openrisc/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4939d 21h /openrisc/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 4940d 01h /openrisc/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4942d 21h /openrisc/
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 4944d 05h /openrisc/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4945d 16h /openrisc/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4945d 17h /openrisc/
424 C++ library, needed for C++ compiler. jeremybennett 4946d 03h /openrisc/
423 Minor typo fixed. jeremybennett 4946d 06h /openrisc/
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 4946d 06h /openrisc/
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".		 julius 4949d 03h /openrisc/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4951d 02h /openrisc/
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.		 julius 4951d 04h /openrisc/
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4951d 04h /openrisc/
417 ORPSoC re-adding doc automake files, this time not symlinks julius 4954d 01h /openrisc/
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 4954d 01h /openrisc/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4954d 01h /openrisc/

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