OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 460

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4947d 01h /openrisc/
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4947d 07h /openrisc/
458 or1ksim testsuite updates julius 4948d 06h /openrisc/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4956d 20h /openrisc/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4956d 21h /openrisc/
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4960d 23h /openrisc/
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4963d 01h /openrisc/
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4963d 12h /openrisc/
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4963d 20h /openrisc/
451 More tidying up. jeremybennett 4967d 16h /openrisc/
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4967d 20h /openrisc/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4969d 16h /openrisc/
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4970d 02h /openrisc/
447 Updates to register order. jeremybennett 4970d 20h /openrisc/
446 gdb-7.2 gdbserver updates. julius 4971d 15h /openrisc/
445 gdbserver update to use kernel port ptrace register definitions. julius 4972d 12h /openrisc/
444 Changes to ABI handling of varargs. jeremybennett 4972d 20h /openrisc/
443 Work in progress on more efficient Ethernet. jeremybennett 4973d 00h /openrisc/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4973d 14h /openrisc/
441 Changes for gdbserver. jeremybennett 4973d 21h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.