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Rev Log message Author Age Path
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4835d 23h /openrisc/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4836d 16h /openrisc/
498 or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, julius 4838d 05h /openrisc/
497 or_debug_proxy updates julius 4839d 01h /openrisc/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4839d 03h /openrisc/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4839d 03h /openrisc/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4849d 21h /openrisc/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4852d 05h /openrisc/
492 ORPSoC VPI interface for modelsim and documentation update julius 4853d 03h /openrisc/
491 ORPSoC or1200_monitor update. julius 4853d 14h /openrisc/
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4857d 19h /openrisc/
489 ORPSoC sw cleanup. Remove warnings. julius 4863d 02h /openrisc/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4863d 03h /openrisc/
487 ORPSoC main software makefile update julius 4866d 00h /openrisc/
486 ORPSoC updates, mainly software, i2c driver julius 4866d 01h /openrisc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4870d 05h /openrisc/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4871d 03h /openrisc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4873d 05h /openrisc/
482 Don't hardcode tool versions in help text olof 4874d 17h /openrisc/
481 OR1200 Update. RTL and spec. julius 4886d 12h /openrisc/

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