OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 522

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
522 Miscellaneous tidy ups. jeremybennett 4928d 13h /openrisc/
521 Tagging the 1.0rc1 release of binutils 2.20.1 for the OpenRISC 1000 julius 4930d 09h /openrisc/
520 Tagging the 1.0rc2 candidate release of Newlib 1.18.0 for the OpenRISC 1000 julius 4931d 06h /openrisc/
519 Tagging the 1.0rc4 candidate release of GCC 4.5.1 julius 4931d 06h /openrisc/
518 Missing parts of checkin from revision 515. Version now 1.0rc4. julius 4931d 07h /openrisc/
517 newlib updates with or1k support functions, libgloss cleanup julius 4932d 00h /openrisc/
516 Tagging the 1.0rc3 release of GCC 4.5.1 for the OpenRISC 1000 jeremybennett 4932d 07h /openrisc/
515 Minor synch with recent changes by Joern. jeremybennett 4932d 07h /openrisc/
514 Changes for version 1.0rc3 for OpenRISC 1000. Various bugs and tests fixed. jeremybennett 4932d 10h /openrisc/
513 Tagging the 1.0rc3 release of GDB 7.2 for the OpenRISC 1000 jeremybennett 4932d 13h /openrisc/
512 Updates for release 1.0rc3 for the OpenRISC 1000. jeremybennett 4932d 13h /openrisc/
511 Tagging the 0.5.1rc1 release of Or1ksim jeremybennett 4933d 12h /openrisc/
510 Updates for release 0.5.1rc1. jeremybennett 4933d 12h /openrisc/
509 Tagging the 0.5.0rc3 release of Or1ksim jeremybennett 4933d 13h /openrisc/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4934d 12h /openrisc/
507 Newlib libgloss board support update. Corresponding GCC port changes to support it. julius 4940d 08h /openrisc/
506 ORPSoC or1200 interrupt and syscall generation test julius 4941d 08h /openrisc/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement
julius 4941d 08h /openrisc/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4958d 04h /openrisc/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4959d 00h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.