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[/] [openrisc/] - Rev 57

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Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5308d 03h	/openrisc/
56	adding generic pll model to orpsoc	julius	5316d 05h	/openrisc/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5318d 19h	/openrisc/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5329d 02h	/openrisc/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5347d 03h	/openrisc/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5347d 23h	/openrisc/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5362d 01h	/openrisc/
50	Adding or32_funcs.S	julius	5362d 05h	/openrisc/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5380d 19h	/openrisc/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5380d 22h	/openrisc/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5390d 06h	/openrisc/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5396d 06h	/openrisc/
45	Orpsoc eth test fix and script error message update	julius	5403d 06h	/openrisc/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5432d 06h	/openrisc/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5456d 03h	/openrisc/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5471d 23h	/openrisc/
41	Update to or1k top	julius	5475d 01h	/openrisc/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5476d 06h	/openrisc/
39	Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update	julius	5480d 06h	/openrisc/
38	Adding binutils, gcc, uClibc patched source and patches	julius	5490d 06h	/openrisc/

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[/] [openrisc/] - Rev 57

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