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Rev Log message Author Age Path
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5186d 17h /openrisc/
75 Fixed toolchain script's cygwin ncurses check julius 5191d 19h /openrisc/
74 Toolchain script fix for ncurses header checking julius 5209d 22h /openrisc/
73 toolchain script error fix julius 5209d 23h /openrisc/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5212d 20h /openrisc/
71 ORPSoC board builds, adding readmes julius 5229d 03h /openrisc/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5233d 07h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5233d 08h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5236d 00h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5236d 03h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5256d 01h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5260d 07h /openrisc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5263d 02h /openrisc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5272d 23h /openrisc/
62 This material is part of the separate website downloads directory. jeremybennett 5284d 02h /openrisc/
61 The build directory should not be part of the SVN configuration. jeremybennett 5284d 03h /openrisc/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5290d 20h /openrisc/
59 Toolchain install script gcc patch change and gdb configure change julius 5311d 20h /openrisc/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5314d 19h /openrisc/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5319d 23h /openrisc/

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