OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 85

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5278d 16h /openrisc/
84 Remove duplicated directories. jeremybennett 5278d 16h /openrisc/
83 Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. jeremybennett 5279d 06h /openrisc/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5279d 07h /openrisc/
81 Directory no longer used. jeremybennett 5279d 07h /openrisc/
80 Add missing configuration files to SVN. jeremybennett 5279d 11h /openrisc/
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5291d 12h /openrisc/
78 Fixed typo in Silos workaround script rherveille 5292d 07h /openrisc/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour
rherveille 5292d 07h /openrisc/
76 Added: +libext+.v
Added: +incdir+.
rherveille 5293d 07h /openrisc/
75 Fixed toolchain script's cygwin ncurses check julius 5298d 09h /openrisc/
74 Toolchain script fix for ncurses header checking julius 5316d 12h /openrisc/
73 toolchain script error fix julius 5316d 13h /openrisc/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5319d 10h /openrisc/
71 ORPSoC board builds, adding readmes julius 5335d 16h /openrisc/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5339d 21h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5339d 22h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5342d 14h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5342d 17h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5362d 15h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.