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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 493

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Rev Log message Author Age Path
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4876d 12h /openrisc/
492 ORPSoC VPI interface for modelsim and documentation update julius 4877d 10h /openrisc/
491 ORPSoC or1200_monitor update. julius 4877d 21h /openrisc/
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4882d 03h /openrisc/
489 ORPSoC sw cleanup. Remove warnings. julius 4887d 10h /openrisc/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4887d 10h /openrisc/
487 ORPSoC main software makefile update julius 4890d 08h /openrisc/
486 ORPSoC updates, mainly software, i2c driver julius 4890d 08h /openrisc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4894d 13h /openrisc/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4895d 11h /openrisc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4897d 13h /openrisc/
482 Don't hardcode tool versions in help text olof 4899d 01h /openrisc/
481 OR1200 Update. RTL and spec. julius 4910d 19h /openrisc/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4911d 17h /openrisc/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4912d 16h /openrisc/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4914d 08h /openrisc/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4914d 16h /openrisc/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4915d 10h /openrisc/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4915d 12h /openrisc/
474 uC/OS-II port linker flags updated. julius 4915d 18h /openrisc/

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