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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 649

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649 porting some of standard demo tasks

fix serial port(UART) interrupt handler		 filepang 4651d 06h /openrisc/
648 docs: OR1K architecture now labeled as revision 0 in draft spec julius 4654d 02h /openrisc/
647 or1200: update documentation to go with recent rtl commits julius 4654d 02h /openrisc/
646 Support ORSoC FT4232 board by using second JTAG; should make a command line option. yannv 4657d 12h /openrisc/
645 or1200: Specification document source now in asciidoc format. ODT and MS Word format documents deprecated, PDF regenerated julius 4672d 01h /openrisc/
644 or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled julius 4672d 02h /openrisc/
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4672d 02h /openrisc/
642 or1200: add carry, overflow bits, and range exception julius 4672d 03h /openrisc/
641 or1200: fix serial multiply/divide bug julius 4672d 03h /openrisc/
640 or1200: add l.ext instructions, fix a MAC bug julius 4672d 03h /openrisc/
639 or1200: or1200_dpram.v change task set_gpr to function julius 4672d 03h /openrisc/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4675d 18h /openrisc/
637 porint parallel port(gpio) management task filepang 4678d 07h /openrisc/
636 porting serial port management task, interrupt hander filepang 4678d 07h /openrisc/
635 Patch for http://bugzilla.opencores.org/show_bug.cgi?id=69.

* config/or32/linux-elf.h <TARGET_OS_CPP_BUILTINS>: Defined, based
on LINUX_TARGET_OS_CPP_BUILTINS copied from linux.h.		 jeremybennett 4679d 11h /openrisc/
634 orpsoc: atlys: autoregenerate coregen cores

Instead of keeping binary .ngc files of the coregen
generated cores, use coregen to generate them from the .xco
and .cgp file		 stekern 4680d 18h /openrisc/
633 orpsoc: add Digilent Atlys spartan6 board README

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4680d 18h /openrisc/
632 orpsoc: add Digilent Atlys spartan6 board sw include file

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4680d 18h /openrisc/
631 orpsoc: add Digilent Atlys spartan6 board testbench

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4680d 18h /openrisc/
630 orpsoc: add Digilent Atlys spartan6 board backend

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4680d 18h /openrisc/

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