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Subversion Repositories openrisc_2011-10-31

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Rev Log message Author Age Path
81 Directory no longer used. jeremybennett 5198d 13h /openrisc/
80 Add missing configuration files to SVN. jeremybennett 5198d 16h /openrisc/
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5210d 17h /openrisc/
78 Fixed typo in Silos workaround script rherveille 5211d 13h /openrisc/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5211d 13h /openrisc/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5212d 12h /openrisc/
75 Fixed toolchain script's cygwin ncurses check julius 5217d 15h /openrisc/
74 Toolchain script fix for ncurses header checking julius 5235d 18h /openrisc/
73 toolchain script error fix julius 5235d 19h /openrisc/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5238d 16h /openrisc/
71 ORPSoC board builds, adding readmes julius 5254d 22h /openrisc/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5259d 03h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5259d 04h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5261d 19h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5261d 22h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5281d 20h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5286d 02h /openrisc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5288d 22h /openrisc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5298d 19h /openrisc/
62 This material is part of the separate website downloads directory. jeremybennett 5309d 22h /openrisc/

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